The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device comprising a memory cell array and a circuit region in which a plurality of circuits are arranged.
JP-A 2000-243085 discloses a semiconductor memory device provided with a memory array and a circuit region, such as a sense amplifier region.
The disclosed semiconductor memory device further comprises a plurality pairs of complementary bit lines extending along a BL direction, a plurality of word lines extending along a WL direction perpendicular to the BL direction, a first line for supplying a first voltage, a second line for supplying a second voltage, a first common source line and a second common source line.
The memory array and the sense amplifier region are arranged in the BL direction. The sense amplifier region includes a plurality of sense amplifier aligned in the WL direction. The sense amplifier has sense nodes which are in contact with the complementary bit lines, respectively. Moreover, the sense amplifier has a first node and a second node which are in contact with the first and the second common source lines, respectively.
The sense amplifier region further includes a first region and a second region. The first region is provided with a plurality of first switches for connecting the first line to the first common source line. The second region is provided with a plurality of second switches for connecting the second line to the second common source line. The first switches and the second switches are aligned along the WL direction, respectively.
In the disclosed semiconductor memory device, the first and the second regions arranged along the BL direction are required for arranging the first and the second circuits along the WL direction.
It is an object of the present invention to provide a semiconductor memory device comprising an effectively utilized circuit region compared with conventional techniques.